发明名称 Processor having compressed and uncompressed instructions and method of instruction execution
摘要 A microprocessor includes one or more memories configured to hold microcode instructions, wherein at least a portion of the microcode instructions are compressed. The microprocessor also includes a decompression unit configured to decompress the compressed microcode instructions after being fetched from the one or more memories and before being executed. A method includes receiving from a memory a first N-bit wide microcode word, determining whether or not a predetermined portion of the first N-bit wide microcode word is a predetermined value, if the predetermined portion is not the predetermined value, decompressing the first N-bit wide microcode word to generate an M-bit wide microcode word, and if the predetermined portion is the predetermined value, receiving from the memory a second N-bit wide microcode word and joining portions of the first and second N-bit wide microcode words to generate the M-bit wide microcode word.
申请公布号 EP2863302(A1) 申请公布日期 2015.04.22
申请号 EP20140151813 申请日期 2014.01.20
申请人 VIA TECHNOLOGIES, INC. 发明人 HENRY, G. GLENN;PARKS, TERRY;BEAN, BRENT
分类号 G06F9/318 主分类号 G06F9/318
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