| 摘要 |
<p>A method of clock domain crossing for a pipelined process in an integrated circuit comprises; in a first clock domain, storing an element of control information in a control queue, and after a pre-set number of clock events of the first clock have passed, storing an associated element of data in a data queue. The method further comprises, in a second clock domain, reading the element of control information after a pre-determined delay, and then reading the element of data after the pre-set number of clock events have occurred for the second clock. This method preserves or maintains an offset (of a number of clock cycles) between control or configuration information and the data it is paired with. The pre-determined delay ensures that the control information is not read too early, when the associated data is not available to be read after the required offset. This problem might occur when the second clock has a higher frequency than the first clock. The length of the pre-determined delay might depend on the ratio of the two clocks and the offset between the paired data. The queues might be a FIFO buffers.</p> |
