Two-terminal memory cell and semiconductor memory device based on different states of stable current

摘要

A two-terminal memory cell includes a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, and a second N-type semiconductor layer arranged in sequence. A first data state may be stored in the memory cell by applying a forward bias, which is larger than a punch-through voltage VBO, between the first P-type semiconductor layer and the second N-type semiconductor layer. A second data state may be stored in the memory cell by applying a reverse bias, which is approaching to the reverse breakdown region of the memory cell, between the first P-type semiconductor layer and the second N-type semiconductor layer. In this way, the memory cell may be effectively used for data storage.

主权项

1. A two-terminal memory cell including an anode terminal and a cathode terminal, the memory cell comprising:
a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, and a second N-type semiconductor layer arranged in sequence, wherein the first P-type semiconductor layer forms the anode terminal and the second N-type semiconductor layer forms the cathode terminal, wherein the memory cell is configured to exhibit different states of stable current flowing from the anode terminal to the cathode terminal at a same bias voltage across the anode terminal and the cathode terminal based on different data states stored therein, the data states include a first data state where the memory cell exhibits a relatively large stable current at the bias voltage, wherein the first data state is stored in the memory cell by applying a forward bias, which is larger than a punch-through voltage VBO, between the first P-type semiconductor layer and the second N-type semiconductor layer, and a second data state where the memory cell exhibits a relatively small stable current at the bias voltage, wherein the second data state is stored in the memory cell by applying a reverse bias, which is approaching to a reverse breakdown region of the memory cell, between the first P-type semiconductor layer and the second N-type semiconductor layer.