Systems and methods for error detection and correction in a memory module which includes a memory buffer

摘要

The present systems include a memory module containing a plurality of RAM chips, typically DRAM, and a memory buffer arranged to buffer data between the DRAM and a host controller. The memory buffer includes an error detection and correction circuit arranged to ensure the integrity of the stored data words. One way in which this may be accomplished is by computing parity bits for each data word and storing them in parallel with each data word. The error detection and correction circuit can be arranged to detect and correct single errors, or multi-errors if the host controller includes its own error detection and correction circuit. Alternatively, the locations of faulty storage cells can be determined and stored in an address match table, which is then used to control multiplexers that direct data around the faulty cells, to redundant DRAM chips in one embodiment or to embedded SRAM in another.

主权项

1. A memory system, comprising:
a plurality of RAM chips; a memory buffer arranged to buffer n-bit data and/or command words being written to or read from said plurality of RAM chips by a host controller; an address match table which stores the addresses of faulty storage cells within said RAM chips; memory storage devices embedded within said memory buffer and distinct from said RAM chips; a plurality of bi-directional multiplexers which convey data words from said host controller to said embedded memory storage devices or said RAM chips when a write operation is performed, and from said embedded memory storage devices or said RAM chips to said host controller when a read operation is performed, each of said embedded memory storage devices connected to a respective one of said bi-directional multiplexers; said address match table arranged to:
receive addresses for read and write operations as generated by said host controller;compare each received address to the addresses stored in said address match table; andcontrol said multiplexers such that one or more bits of a data word are written to and read from said embedded memory storage devices when the address associated with said data word matches that of a faulty storage cell, such that the flow of data is directed around said faulty storage cell.