Control scheme for 3D memory IC

摘要

The present invention discloses a control scheme for 3D memory IC that includes a master chip and at least one slave chip. The master chip includes a main memory core, a first local timer, an I/O buffer, a first pad and a second pad. The at least one slave chip is stacked with the master chip. Each of the slave chip includes a slave memory core, a second local timer and a third pad. A first TSV is coupled to the first pad and the third pad. A logic control circuit layer includes a logic control circuit and a fourth pad, and the logic control circuit is coupled to the fourth pad. A second TSV is coupled to the second pad and the fourth pad.

主权项

1. A control scheme for 3D memory IC, comprising:
a master chip layer; including a master memory core, a first timer, an input/output buffer, a first contact pad and a second contact pad; at least one slave chip layer, stacked with said master chip layer, wherein each of said at least one slave chip layer respectively includes a slave memory core, a second timer and a third contact pad; a first through-silicon-via (TSV), coupled to said first contact pad and said third contact pad; a logic control circuit layer, including a logic control circuit and a fourth contact pad, wherein said logic control circuit is coupled to said fourth contact pad; a second through-silicon-via (TSV), coupled to said second contact pad and said fourth contact pad; and said first timer and said second timer are local timers to separately operate timing control for each of the master chip layer and the at least one slave chip layer, for transmitting signals by self-timed differential-TSV (STDT).