发明名称 |
LED with improved injection efficiency |
摘要 |
A light emitting device and method for making the same is disclosed. The light-emitting device includes an active layer sandwiched between a p-type semiconductor layer and an n-type semiconductor layer. The active layer emits light when holes from the p-type semiconductor layer combine with electrons from the n-type semiconductor layer therein. The active layer includes a number of sub-layers and has a plurality of pits in which the side surfaces of a plurality of the sub-layers are in contact with the p-type semiconductor material such that holes from the p-type semiconductor material are injected into those sub-layers through the exposed side surfaces without passing through another sub-layer. The pits can be formed by utilizing dislocations in the n-type semiconductor layer and etching the active layer using an etching atmosphere in the same chamber used to deposit the semiconductor layers without removing the partially fabricated device. |
申请公布号 |
US9012953(B2) |
申请公布日期 |
2015.04.21 |
申请号 |
US201414175623 |
申请日期 |
2014.02.07 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Lester Steven;Ramer Jeff;Wu Jun;Zhang Ling |
分类号 |
H01L33/00;H01L33/22;H01L21/02;H01L33/20;H01L33/06;H01L33/02;H01L33/32 |
主分类号 |
H01L33/00 |
代理机构 |
Hogan Lovells US LLP |
代理人 |
Hogan Lovells US LLP |
主权项 |
1. A light emitting device comprising:
an n-type semiconductor layer, the n-type semiconductor layer including random dislocations; an active layer comprising a plurality of sub-layers on the n-type semiconductor layer, the active layer including pits of a density between 107 cm−2 and 1010 cm−2 located on the random dislocations, a plurality of the sub-layers having sidewalls that are bounded by the pits and exposed to the pits, bottoms of the pits located in the n-type semiconductor layer; a p-type semiconductor layer over the active layer, the p-type semiconductor layer extending into the pits and contacting the exposed sidewalls of the sub-layers and an upper surface of the active layer; and contact electrodes configured to apply a potential difference between the p-type semiconductor layer and the n-type semiconductor layer. |
地址 |
Tokyo JP |