Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor

摘要

A memory array including a plurality of memory cells. In one embodiment, each memory cell is coupled to an electrically conductive gate material. A word line is coupled to the gate material at a contact interface level. A pair of pillars is comprised of an insulating material that extends below the contact interface level. Also, a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes depositing and etching gate material to partially fill a space between the pillars and to form a word line for the memory cells, forming a pair of pillars comprised of an insulating material and depositing a gate contact between the pair of pillars such that the gate contact electrically couples the gate material at a contact interface level and the insulating material extends below the contact interface level.

主权项

1. A memory array comprising:
a plurality of memory cells, each of the memory cells electrically coupled in parallel at its respective gate contact to an electrically conductive gate material; a word line electrically coupled to the gate material at a contact interface level; and a pair of pillars, each of the pair of pillars including an electrically insulating material over a doped silicon material, wherein a first pillar of the pair of pillars is disposed on a first side of the gate contact and a second pillar of the pair of pillars is disposed on a second side of the gate contact such that the electrically insulating material extends below the contact interface level.