发明名称 M-pair mode protection switching
摘要 A communication comprises a plurality of digital subscriber line (DSL) links, a first node having at least one application port configured for an elastic service and a plurality of DSL ports, and a second node having at least one application port configured for an elastic service and a plurality of DSL ports. Each of the first and second nodes is configured to interleave data received over the at least one application port across the plurality of DSL ports, each DSL port allocated a set of DSL timeslots for transport of the data received over the at least one application port. When a failure is detected on one of the DSL links, each of the first and second nodes is configured to interleave the data received over the at least one application port across the remaining DSL ports not connected to the failed DSL link without adjusting the set of DSL timeslots allocated to each of the remaining DSL ports for transport of the data from the at least one application port.
申请公布号 US9013982(B2) 申请公布日期 2015.04.21
申请号 US201113187306 申请日期 2011.07.20
申请人 ADC DSL Systems, Inc. 发明人 Polland Joe;Powers Clifton;Sharma Manish;Anne Laxman R.;Chan Yiu Lam
分类号 G01R31/08;H04L12/28;H04M11/06 主分类号 G01R31/08
代理机构 Fogg & Powers LLC 代理人 Fogg & Powers LLC
主权项 1. A communication unit comprising: at least one application port configured for an elastic service; a plurality of digital subscriber line (DSL) transceivers each coupled to a respective DSL link; and a processing circuit coupled to the at least one application port and the plurality of DSL transceivers, the processing circuit configured to provide a copy of data received from the at least one application port to each of the plurality of DSL transceivers via a respective data stream comprising timeslots, the processing circuit further configured to provide a timeslot map to each of the DSL transceivers, the timeslot map indicating which of the timeslots in the data stream are to be processed by each respective DSL transceiver such that the data from the at least one application port is interleaved across the plurality of DSL transceivers; wherein when a failure is detected on one of the DSL links, the processing circuit is configured to update the timeslot map such that the data from the at least one application port is interleaved across the remaining DSL transceivers not connected to the failed DSL link without changing the respective number of timeslots allocated to each remaining DSL transceiver.
地址 Berwyn PA US