发明名称 |
Semiconductor device and method of manufacturing same |
摘要 |
A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area. |
申请公布号 |
US9012285(B2) |
申请公布日期 |
2015.04.21 |
申请号 |
US201313765266 |
申请日期 |
2013.02.12 |
申请人 |
Fujitsu Semiconductor Limited |
发明人 |
Usujima Akihiro;Satoh Shigeo |
分类号 |
H01L21/8234 |
主分类号 |
H01L21/8234 |
代理机构 |
Fujitsu Patent Center |
代理人 |
Fujitsu Patent Center |
主权项 |
1. A method of manufacturing a semiconductor device, the method comprising:
forming an element isolation region in a semiconductor substrate to represent a first device region and a second device region having a larger area than the first device region; forming a first gate electrode having a first width in the first device region; forming a second gate electrode having a third width in the second device region; forming a first sidewall spacer having a second width on a sidewall of the first gate electrode; forming a second sidewall spacer having a fourth width, which is wider than the second width, on a sidewall of the second gate electrode; implanting first impurities into the first device region, using the first gate electrode and the first sidewall spacer as masks, to form a first impurity region; implanting second impurities into the second device region, using the second gate electrode and the second sidewall spacer as masks, to form a second impurity region; activating the first impurities and the second impurities by heat treatment; forming a silicide film over the first impurity region and the second impurity region after the heat treatment; forming an interlayer insulation film over the silicide film; and forming a first contact plug which penetrates the interlayer insulation film and the silicide film and couples with one of the first impurity region and the second impurity region, wherein a first length of the first impurity region in a direction perpendicular to the first gate electrode is shorter than a second length of the second impurity region in a direction perpendicular to the second gate electrode, and an impurity concentration in the first impurity region is substantially equal to an impurity concentration in the second impurity region. |
地址 |
Yokohama JP |