Multiplierless coprocessor for difference of Gaussian (DoG) calculation

摘要

A hardware architecture is applied to the calculation of a Difference-of-Gaussian filter, which is typically employed in image processing algorithms. The architecture has a modular structure to easily allow the matching of the desired delay/area ratio as well as a high computational accuracy. A new solution is provided for the implementation of multiply-accumulators which allows a significant reduction of area with respect to the conventional architectures.

主权项

1. A multiplier accumulator circuit comprising:
a first lookup table configured to provide Bachet terms in response to an input pixel value; a plurality of second lookup tables configured to provide intermediate values in response to the Bachet terms; and a set of full adders configured to sum the inte mediate values from the second lookup tables and to provide an output value representative of the input pixel value multiplied by a coefficient.