Multiple device voltage electrostatic discharge clamp

摘要

A multiple device voltage electrostatic discharge (ESD) clamp includes a trigger circuit, first and second inverters, and an ESD discharge path. The trigger circuit includes a resistor having a first terminal electrically connected to a first voltage supply node, and a capacitor having a first terminal electrically connected to a second voltage supply node. The first inverter has an input terminal electrically connected to second terminals of the resistor and the capacitor. The second inverter has a power terminal electrically connected to an output terminal of the first inverter. The ESD discharge path has a first end electrically connected to the first voltage supply node, and a second end electrically connected to a third voltage supply node, and includes a first transistor controlled by the first inverter, and a second transistor controlled by the second inverter.

主权项

1. A multiple device voltage electrostatic discharge (ESD) clamp comprising:
a trigger circuit comprising:
a resistor having a first terminal electrically connected to a first voltage supply node; anda capacitor having a first terminal electrically connected to a second voltage supply node, and a second terminal connected to a second terminal of the resistor; a first inverter having an input terminal electrically connected to the second terminals of the resistor and the capacitor, the first inverter having a first power terminal and a second power terminal, the first voltage supply node electrically connected to supply a first voltage to the first power terminal of the first terminal, the second voltage supply node electrically connected to supply a second voltage to the second power terminal of the first inverter; a second inverter having a power terminal, wherein an output terminal of the first inverter is electrically connected to drive the first power terminal of the second inverter, and wherein the second voltage supply node is electrically connected to supply the second voltage to an input terminal of the second inverter; and an ESD discharge path having a first end electrically connected to the first voltage supply node, and a second end electrically connected to a third voltage supply node, the ESD discharge path comprising:
a first transistor controlled by the first inverter; anda second transistor controlled by the second inverter.