发明名称 |
Testing a decision feedback equalizer (‘DFE’) |
摘要 |
Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal. |
申请公布号 |
US9014254(B2) |
申请公布日期 |
2015.04.21 |
申请号 |
US201313921470 |
申请日期 |
2013.06.19 |
申请人 |
International Business Machines Corporation |
发明人 |
Atwood Eugene R.;Baecher Matthew B.;Chen Minhan;Cranford, Jr. Hayden C.;Kelly William R.;Rasmus Todd M. |
分类号 |
H03K5/159;H04B17/00 |
主分类号 |
H03K5/159 |
代理机构 |
Biggers Kennedy Lenart Spraggins LLP |
代理人 |
Lenart Edward J.;Schnurmann H. Daniel;Biggers Kennedy Lenart Spraggins LLP |
主权项 |
1. A method of testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, the method comprising:
preventing a differential data signal from being received by the summing amplifier; and testing a plurality of taps including, iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined latch value including setting an amplitude offset for the summing amplifier to a predetermined amplifier initialization value and waiting a predetermined number of clock cycles; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal. |
地址 |
Armonk NY US |