Channel SiGe removal from PFET source/drain region for improved silicide formation in HKMG technologies without embedded SiGe

摘要

When forming sophisticated P-channel transistors, a semiconductor alloy layer is formed on the surface of the semiconductor layer including the transistor active region. When a metal silicide layer is formed contiguous to this semiconductor alloy layer, an agglomeration of the metal silicide layer into isolated clusters is observed. In order to solve this problem, the present invention proposes a method and a semiconductor device wherein the portion of the semiconductor alloy layer lying on the source and drain regions of the transistor is removed before formation of the metal silicide layer is performed. In this manner, the metal silicide layer is formed so as to be contiguous to the semiconductor layer, and not to the semiconductor alloy layer.

主权项

1. A method of forming a semiconductor structure adapted to be formed as a P-channel FET, said method comprising:
forming a semiconductor layer comprising at least one active region, said semiconductor layer comprising an upper surface; depositing a semiconductor alloy layer onto said upper surface of said semiconductor layer; forming a gate electrode structure onto said semiconductor alloy layer; forming source and drain extension regions in said at least one active region of said semiconductor layer; after forming said source and drain extension regions in said at least one active region of said semiconductor layer, removing one or more predetermined portions of said semiconductor alloy layer so as to expose one or more surface portions of said semiconductor layer; and forming a metal silicide layer having an interface with said semiconductor layer, said metal silicide layer being formed after removing said one or more predetermined portions of said semiconductor alloy layer.