METHOD AND SYSTEM FOR THREE-DIMENSIONAL LAYOUT DESIGN OF INTEGRATED CIRCUIT ELEMENTS IN STACKED CMOS

摘要

A method includes providing a design of a semiconductor device such as a stacked CMOS device comprising a plurality of circuit elements to be assigned into a layout of a plurality of tiers, and identifying at least one first type of circuit element within the plurality of circuit elements based on at least one predetermined criterion. Each respective one of the at least one first type of circuit element is to be assigned to a respective designated one of the plurality of tiers. The method further includes dividing the remainder of the plurality of circuit elements into at least two groups of circuit elements based on circuit density, and assigning the at least one first type of circuit element and the at least two groups of circuit elements to respectively different ones of the plurality of tiers of the semiconductor device.

主权项

1. A method comprising:
providing a design of a semiconductor device comprising a plurality of circuit elements to be assigned into a layout of a plurality of tiers; identifying at least one first type of circuit element within the plurality of circuit elements, based on at least one predetermined criterion; dividing the remainder of the plurality of circuit elements into at least two groups of circuit elements based on circuit density; assigning a maximum density gradient to a respective tier for each of the at least two groups of circuit elements; and assigning the at least one first type of circuit element and the at least two groups of circuit elements to respectively different ones of the plurality of tiers of the semiconductor device.