CHIP STACK CACHE EXTENSION WITH COHERENCY

摘要

By arranging dies in a stack such that failed cores are aligned with adjacent good cores, fast connections between good cores and cache of failed cores can be implemented. Cache can be allocated according to a priority assigned to each good core, by latency between a requesting core and available cache, and/or by load on a core.

主权项

1. A cache management method for a semiconductor device stack of at least two dies, each die including at least two computing devices, each computing device including at least one core, each core including a local cache, and each die including at least one shared cache connected to at least one core of the respective die, the method comprising:
testing each core; responsive to a core failing the testing, identifying the core as a failed core; responsive to a core passing the testing, identifying the core as a good core; stacking the at least two dies such that a good core of a first die is aligned with a failed core of at least one adjacent die; and connecting a failed core local cache of each failed core to at least a first aligned good core for primary use by the at least a first aligned good core.