MEMORY ARRAY ARCHITECTURES HAVING MEMORY CELLS WITH SHARED WRITE ASSIST CIRCUITRY

摘要

A memory device includes a memory array having a plurality of memory cells each having first and second power supply nodes, first and second virtual power supply nodes, a latch circuit, and a write assist circuit. The latch circuit includes a first and second inverters in a cross-coupled inverter configuration. The first inverter is connected between the first virtual power supply node and the second power supply node, and the second inverter is connected between the second virtual power supply node and the second power supply node. The write assist circuit selectively supplies power to the first and second virtual power supply nodes during memory access operations, and is controlled by a first control signal to switchably connect the first power supply node to and from the first and second virtual power supply nodes, and a second control signal to switchably connect the one or both of the first and second virtual power supply nodes to a virtual power supply node of an adjacent memory cell of an adjacent row in the memory array.

主权项

1. A memory device comprising:
a memory array comprising a plurality of memory cells, wherein at least two or more memory cells each comprise: a first power supply node, a second power supply node, a first virtual power supply node, and a second virtual power supply node; a latch circuit comprising a first inverter and a second inverter, which are connected in a cross-coupled inverter configuration, wherein the first inverter is connected between the first virtual power supply node and the second power supply node, and wherein the second inverter is connected between the second virtual power supply node and the second power supply node; and a write assist circuit to selectively supply power to the first and second virtual power supply nodes of the memory cell during access operations of the memory cell, wherein the write assist circuit is controlled by a first control signal to switchably connect and disconnect the first power supply node to and from the first and second virtual power supply nodes of the memory cell, and wherein the write assist circuit is controlled by a second control signal to switchably connect and disconnect at least one of the first and second virtual power supply nodes of the memory cell to a virtual power supply node of an adjacent memory cell of an adjacent row in the memory array.