Cost Effective Method of Forming Embedded DRAM Capacitor

摘要

A high capacitance embedded metal interconnect capacitor and associated fabrication processes are disclosed for using a directional barrier metal formation sequence in a dual damascene copper process to form multi-layer stacked copper interconnect structure having reduced barrier metal layer formation at the bottom of each via hole so that the multi-layer stacked copper interconnect structure may be readily removed and replaced with high capacitance MIM capacitor layers.

主权项

1. An integrated circuit device comprising:
a semiconductor substrate comprising one or more active circuits and at least a first conductive contact structure; and a stacked interconnect structure formed on the semiconductor substrate with multiple interconnect levels, each interconnect level comprising:
a metal-based damascene interconnect structure comprising a first directional diffusion barrier liner layer located on a sidewall of a first opening in one or more patterned dielectric layers; anda damascene capacitor structure comprising a second directional diffusion barrier liner layer located on a sidewall of a second opening in the one or more patterned dielectric layers and a plurality of capacitor layers formed on the directional diffusion barrier liner layer, where the metal-based damascene interconnect structures in each interconnect level are aligned for electrical connection to the one or more active circuits, and where the damascene capacitor structures in each interconnect level are aligned to form a single capacitor having a first capacitor plate electrically connected to the first conductive contact structure.