| 摘要 |
The present invention provides a semiconductor device capable of resetting abnormal pipe input and output control signals which may occur in data training in which the reset operation is performed in a period except for a write period, and a semiconductor system comprising the same. The semiconductor device according to the present invention may comprise: a pipe latch configured to sequentially latch data in response to a pipe input control signal and, sequentially output data in response to a pipe output control signal; a pipe latch control unit configured to generate pipe input and output control signals in response to a command signal and latency information, and control input and output operations of the pipe latch using the pipe input and output control signals; and an error detection unit configured to receive the pipe input and output control signals, and detect a latency error, and reset, in response to the latency error, the pipe input and output control signals of the pipe latch control unit. |
