DISTRIBUTING MULTIPLEXING LOGIC TO REMOVE MULTIPLEXOR LATENCY ON THE OUTPUT PATH FOR VARIABLE CLOCK CYCLE, DELAYED SIGNALS

摘要

A controller sets a selector register of programmable delay signal logic is to a value equal to a required number of clock cycles of delay for signals output from an integrated circuit to an external memory. The controller controls a selection of additional logic along the output path to perform on the delayed signal within a clock cycle without any latency added to the output path by delay signal logic outputting the delayed signal. The controller waits required number of clock cycles after setting the selector register before using the delayed signal output by the delay signal logic onto an output path.

主权项

1. A method for controlling programmable delay signal logic, comprising:
setting a selector register of programmable delay signal logic to a value equal to a required number of clock cycles of delay for signals output from an integrated circuit to an external memory, wherein the programmable delay signal logic is programmable by the selector register value to receive a signal and output a delayed signal delayed by the required number of clock cycles of delay on a rising edge of a clock cycle from among 1 to N programmable clock cycles of delay; controlling a selection of additional logic along the output path to perform on the delayed signal within a clock cycle without any latency added to the output path by delay signal logic outputting the delayed signal, wherein the delay signal logic comprises at least one multiplexor distributed along a delay path of the delay signal logic, wherein each at least one multiplexor is configured to receive two inputs and output one of the two inputs, wherein each at least one multiplexor is configured to select one of the two inputs according to the value set in the selector register to control the required number of clock cycles of delay added to the signal from 1 to N clock cycles, wherein the at least one multiplexor comprises N−1 multiplexors, and at least two latches distributed along the delay path of the delay signal logic, wherein each at least one latch is configured to add a clock cycle of delay, wherein the at least two latches comprise N latches, wherein the signal is initially simultaneously distributed both as input to a first latch of the at least two latches positioned in the delay path and as one of the two inputs to each at least one multiplexor, wherein a terminating latch from among the at least two latches is configured to output the signal delayed by the required number of clock cycles; and waiting the required number of clock cycles after setting the selector register before using the delayed signal output by the delay signal logic onto an output path.