| 发明名称 |
CIRCUIT FOR TESTING INTEGRATED CIRCUITS |
| 摘要 |
An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode. |
| 申请公布号 |
US2015106672(A1) |
申请公布日期 |
2015.04.16 |
| 申请号 |
US201414575207 |
申请日期 |
2014.12.18 |
| 申请人 |
STMICROELECTRONICS INTERNATIONAL N.V. |
发明人 |
Kulkarni Anirudha;SINGH JASVIR |
| 分类号 |
G01R31/3177 |
主分类号 |
G01R31/3177 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
AMSTERDAM NL |
