| 摘要 |
The present invention relates to semiconductor technology, and provides methods for erasing, reading and programming a flash memory. In the present invention, when an erase operation is performed on the flash memory, for a sector selected for the erase operation, its N-type well is applied with a voltage of 8V˜12V, its bit line is applied with a voltage of 4V˜6V, and its word line is applied with a voltage of −7V˜−10V. When a read operation is performed on the flash memory, for a sector selected for the read operation, its N-type well is applied with a VCC voltage; for a flash memory cell selected for the read operation, its bit line is applied with the VCC voltage, and its source line is applied with a voltage of 0V. When a program operation is performed on the flash memory, for a flash memory cell selected for the program operation, its bit line is applied with a voltage of VCC−6.5V˜VCC−4.5V, and its bit line is applied with a voltage of VCC+6V˜VCC+9V. In full consideration of factors including the chip manufacturing process, chip circuit design, chip quality and cost, optimal operating conditions fit for erasing, reading and programming, a NOR-type embedded 2T PMOS flash memory are determined. |
| 主权项 |
1. A method for erasing a flash memory comprising an array of at least one sector, each sector comprising an N-type well and a plurality of flash memory cells coupled in a matrix in the N-type well, wherein
each flash memory cell comprises a select gate PMOS transistor and a control gate PMOS transistor with a floating gate, and a first electrode of the select gate PMOS transistor is coupled to a second electrode of the control gate PMOS transistor; in the matrix coupled by the flash memory cells, the second electrodes of the select gate PMOS transistors in the same column are coupled together to form a first control line, and gates of the control gate PMOS transistors in the same row are coupled together to form a second control line; and the select gate PMOS transistor has a gate oxide layer with a thickness of 8 nm to 11 nm and a channel with a length of 100 nm to 300 nm; the control gate PMOS transistor has a gate oxide with a thickness of 8 nm to 11 nm, an ONO thin film dielectric layer with a thickness of 10 nm to 20 nm and a channel with a length of 100 nm to 300 nm; the method comprising: when performing an erase operation, applying a voltage of 8 to 12 V to the N-type well of a sector selected for the erase operation, a voltage of 4 to 6 V to the first control line of the selected sector and a voltage of −10 to −7 V to the second control line of the selected sector; wherein the first electrode is a source and the second electrode is a drain, or the first electrode is the drain and the second electrode is the source. |
