发明名称 |
SEMICONDUCTOR MEMORY DEVICE |
摘要 |
This semiconductor memory device comprises a memory cell array that includes: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; a plurality of memory cells each disposed at an intersection of the plurality of first lines and the plurality of second lines and including a variable resistance element; and a select transistor respectively connected to an end of the plurality of first lines. The select transistor includes a gate electrode, a gate insulating film, and a conductive layer. Moreover, one end of that conductive layer is connected to the end of the first line, and a non-linear resistance layer configured from a non-linear material is connected between the first line and the conductive layer. |
申请公布号 |
US2015103582(A1) |
申请公布日期 |
2015.04.16 |
申请号 |
US201414178636 |
申请日期 |
2014.02.12 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
OKAWA Takamasa;TSUKAMOTO Takayuki;MINEMURA Yoichi;KANNO Hiroshi;YOSHIDA Atsushi;TABATA Hideyuki |
分类号 |
H01L27/24;G11C13/00;H01L45/00 |
主分类号 |
H01L27/24 |
代理机构 |
|
代理人 |
|
主权项 |
1. A semiconductor memory device, comprising:
a memory cell array including: first line; second lines intersecting the first line; memory cells disposed at an intersection of the first line and the second lines and including a variable resistance element; and a select transistor respectively connected to an end of the first line, the selector including a gate electrode, a gate insulating film, and a semiconductor layer, one end of the semiconductor layer being connected to the end of the first line, and a non-linear resistance layer disposed between the first line and the semiconductor layer, the non-linear resistance layer being configured from a non-linear material. |
地址 |
Minato-ku JP |