发明名称 Chip Scale Semiconductor Package and Fabricating this
摘要 <p>The present invention relates to a chip scale semiconductor package that is fabricated such that: forming the resin layer on the front/back of wafer wherein liquid resin containing flux component is applied in the state in which bumps or solder balls are formed in I/O terminal of the semiconductor chip that is wafer state; then, forming the protection layer on the integrated circuit (IC) chip of the wafer, wherein the resin layer is dried or in B-stage state; then, attaching the protection layer to the insulation tape of sawing tape and manufacturing the individual semiconductor chip scale package by sawing the wafer. The semiconductor chip-scale package is mounted on the surface of the PCB that is to be used, and the protective layer (resin layer) on the back of the chip has the fluidity due to the heat applied at that moment in which it is flowing down the side of the semiconductor chip-scale package so that the protective layer (protection layer) on the side of the cut chip is formed or the protective layer (resin layer) at the bottom of the chip also has a fluidity so that under-fill between the chip and the circuit board is configured to be comprised.</p>
申请公布号 KR20150041272(A) 申请公布日期 2015.04.16
申请号 KR20130119550 申请日期 2013.10.08
申请人 发明人
分类号 H01L23/28 主分类号 H01L23/28
代理机构 代理人
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