发明名称 Power MOSFET and Methods for Forming the Same
摘要 A device includes a trench extending into a semiconductor region and having a first conductivity type, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer and having an edge portion overlapping the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion contacting the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. A MOS-containing device is at a surface of the semiconductor region.
申请公布号 US2015104917(A1) 申请公布日期 2015.04.16
申请号 US201414574096 申请日期 2014.12.17
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Ng Chun-Wai;Chou Hsueh-Liang;Su Po-Chih;Liu Ruey-Hsin
分类号 H01L29/66 主分类号 H01L29/66
代理机构 代理人
主权项 1. A method comprising: forming a first trench in a semiconductor region, wherein the semiconductor region is of a first conductivity type; forming an implantation mask extending into the trench and covering edges of the trench; performing a tilt implantation to form a Doped Drain (DD) region in the semiconductor region, wherein the DD region is of the first conductivity type; etching the semiconductor region to extend the trench further down into the semiconductor region, wherein the etching is anisotropic, with portions of the DD region located on opposite sides of the trench; after the etching, forming a first dielectric layer lining a bottom and sidewalls of the trench; forming a field plate in the trench and over a bottom portion of the first dielectric layer; forming a second dielectric layer over the field plate; forming a main gate in the trench and over the second dielectric layer; and forming a lateral Metal-Oxide-Semiconductor (MOS) device, wherein the lateral MOS device comprises a gate electrode over the semiconductor region.
地址 Hsin-Chu TW