| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a reconfigurable logic block, a programmable logic circuit device therewith and a technology mapping method which implement a small device area and a low power consumption. <P>SOLUTION: A reconfigurable logic block (K-A<SP POS="POST">2</SP>LUT) with maximally K inputs (x[0]-x[K-1]) includes: a first lookup table 1 with m inputs (y[0]-y[m-1], where m is smaller than K and y belongs to x); a second lookup table 2 with n inputs (z[0]-z[n-1], where n is smaller than K and z belongs to x); a combinational circuit 3 with p inputs (c[0]-c[p-1], where p is smaller than K and c belongs to x); and a selector 4 for selecting either the first lookup table 1 or the second lookup table 2 in accordance with an output of the combinatorial circuit 3. <P>COPYRIGHT: (C)2012,JPO&INPIT</p> |
