发明名称 時間増幅回路及びその特性テストを実行するためのプログラム
摘要 <p>PROBLEM TO BE SOLVED: To provide a time amplification circuit that has a reduced time offset.SOLUTION: According to an embodiment, a time amplification circuit 100 having a plurality of time amplifiers connected in multiple stages includes: a first time amplifier TA1; a second time amplifier TA2 fed with output signals of the first time amplifier; a first switch element SW1 for connecting positive and negative input terminals of TA1; a second switch element SW2 for connecting positive and negative input terminals of TA2; a first flip-flop circuit FF1 for detecting a first offset polarity on the basis of the output signals of TA1; a second flip-flop circuit FF2 for detecting a second offset polarity on the basis of output signals of TA2; and a control circuit 50a for controllingly configuring a series connection if the first and second offset polarities are different and configuring a cross connection if the first and second offset polarities are the same.</p>
申请公布号 JP5703324(B2) 申请公布日期 2015.04.15
申请号 JP20130050319 申请日期 2013.03.13
申请人 发明人
分类号 H03F3/34;H03K5/26 主分类号 H03F3/34
代理机构 代理人
主权项
地址
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