发明名称 高信号レベル対応入出力回路
摘要 <p>A level shifter has at least one of either a pull up or a pull down circuit. The circuit is made of electronic components with reliability limits less than a maximum signal level output by the level shifter. The level shifter also has a timing circuit coupled to at least on of either the pull up or pull down circuit. The timing circuit controls a time of application of an input signal to at least one of either the pull up or pull down circuit preventing a terminal to terminal signal level experienced by the electronic components exceeding the reliability limits.</p>
申请公布号 JP5701939(B2) 申请公布日期 2015.04.15
申请号 JP20130139728 申请日期 2013.07.03
申请人 发明人
分类号 H03K19/0185 主分类号 H03K19/0185
代理机构 代理人
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