发明名称 Interface circuit for transmitting and receiving digital signals between devices
摘要 A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.
申请公布号 US9009335(B2) 申请公布日期 2015.04.14
申请号 US201314098783 申请日期 2013.12.06
申请人 Sony Corporation 发明人 Ichimura Gen;Kikuchi Hidekazu;Nakajima Yasuhisa
分类号 G06F11/00;H04J3/06;H04L25/02;H04L25/493;H04N21/436;H04N21/4363;H04N21/643;H04L7/00 主分类号 G06F11/00
代理机构 Lerner, David, Littenberg, Krumholz & Mentlik, LLP 代理人 Lerner, David, Littenberg, Krumholz & Mentlik, LLP
主权项 1. A transmitting device, comprising: a first transmitting section for transmitting a first signal as a differential signal to an external device through a first transmission line; a second transmitting section for transmitting a second signal, being multiplexed to the first transmission line, as a common-mode signal to the external device; a communication circuit configured to communicate with the external device via a pair of differential transmission lines included in the first transmission line, wherein the communication circuit includes a circuit arranged to bias the transmission line to a first voltage level, thereby notifying the external device of a connection status of its own device by at least one of direct current bias potentials of the pair of differential transmission lines; a receiver for receiving an audio signal from the external device through a second transmission line; and a reproduction circuit configured to reproduce the audio signal, comprising: a first circuit configured to generate an internal clock signal;a second circuit to reconfigure a clock component based on an incoming signal;a third circuit configured to select one of the internal clock signal and the reconfigured clock component for an output; anda fourth circuit configured to read out, based on the output, the audio signal; wherein the reproduction circuit is configured to silence, when an error occurs in the second transmission line, a portion of the audio signal where the error has occurred.
地址 JP
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