发明名称 |
Non-volatile semiconductor memory device |
摘要 |
According to one embodiment, a non-volatile semiconductor memory device comprises a memory cell array and a memory region. The memory cell array has a plurality of physical blocks. Each of the plurality of physical blocks includes a plurality of string units. Each string unit has a plurality of NAND strings that shares a plurality of word lines connected to a plurality of memory cells, respectively. The memory region is disposed to one of the plurality of physical blocks. Each of the plurality of string units configures a first logical block, and when the first logical block is failed, information of the first failed logical block is stored in a first region of the memory region. |
申请公布号 |
US9007836(B2) |
申请公布日期 |
2015.04.14 |
申请号 |
US201313931305 |
申请日期 |
2013.06.28 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Shirakawa Masanobu |
分类号 |
G11C16/14;G11C16/02;G11C29/04;G11C5/06;G11C5/02;G11C16/04;G11C16/08;G11C29/02;G11C29/00;G11C16/10;G11C16/00;G11C29/12;G11C29/44 |
主分类号 |
G11C16/14 |
代理机构 |
Oblon, McClelland, Maier & Neustadt, L.L.P. |
代理人 |
Oblon, McClelland, Maier & Neustadt, L.L.P. |
主权项 |
1. A non-volatile semiconductor memory device comprising:
a memory cell array comprising a plurality of physical blocks, one of the physical blocks comprising a plurality of string units, the string units including a first string unit and a second string unit, the first string unit including a first NAND string, the second string unit including a second NAND string, the first NAND string including a first memory cell and a first select transistor, the second NAND string including a second memory cell and a second select transistor, a gate of the first memory cell being coupled to a gate of the second memory cell, a gate of the first select transistor being coupled to a first line, and a gate of the second select transistor being coupled to a second line, the first line being electrically isolated from the second line, wherein each of the string units configures a first logical block, and when the first logical block has a defect, the information of a first defect logical block is stored in the memory cell array. |
地址 |
Minato-ku JP |