发明名称 |
Successive-approximation-register analog-to-digital converter and method thereof |
摘要 |
A main ADC (analog-to-digital converter) for converting an analog input signal into a digital data, and an auxiliary ADC for converting the same analog input signal into an auxiliary digital data, wherein: the main ADC is a successive-approximation-register (SAR) ADC of a first resolution with a first conversion speed; the auxiliary ADC is of a second resolution with a second conversion speed; the second resolution is lower than the first resolution but the second conversion speed is higher than the first conversion speed; and the main ADC generates the digital data by undergoing a process of successive approximation comprising a plurality of steps including a fast-track step that is based on a value of the auxiliary digital data. |
申请公布号 |
US9007253(B2) |
申请公布日期 |
2015.04.14 |
申请号 |
US201314045821 |
申请日期 |
2013.10.04 |
申请人 |
Realtek Semiconductor Corp. |
发明人 |
Lin Chia-Liang |
分类号 |
H03M1/12;H03M1/38;H03M1/14;H03M1/46 |
主分类号 |
H03M1/12 |
代理机构 |
McClure, Qualey & Rodack, LLP |
代理人 |
McClure, Qualey & Rodack, LLP |
主权项 |
1. An analog-to-digital conversion apparatus, comprising:
a first ADC (analog-to-digital converter) having a first resolution and a first conversion speed, for converting an analog input signal into a first digital signal, based in part on a value of a second digital signal provided to the first ADC, the first ADC comprising:
a bootstrapped controller, for updating a digital code according to a decision signal and the second digital signal and generating the first digital signal based on a final value of the digital code at an end of a first process;a S/H (sample-and-hold) circuit configured to sample the analog input signal into a first voltage;a DAC (digital-to-analog converter) for converting the digital code into a second voltage;a summing circuit configured to generate a third voltage having a magnitude equal to a difference between the first voltage and the second voltage; anda comparator configured to generate the decision signal based on a polarity of the third voltage; and a second ADC of a second resolution and a second conversion speed, for converting the analog input signal into the second digital signal; wherein the second resolution is lower than the first resolution and the second conversion speed is higher than the first conversion speed. |
地址 |
Hsinchu TW |