SRAM global precharge, discharge, and sense

摘要

An SRAM includes a global bit line, an SRAM cell, precharge logic, discharge logic, and sense logic. The SRAM cell stores a first logical value or a second logic value and is coupled to the global bit line. The precharge logic may charge the global bit line to a precharge voltage for a non-read operation and a boosted voltage that is greater than a reference voltage for a read operation. The discharge logic may either maintain the global bit line at the boosted voltage for the first logical value or discharge the global bit line to a discharge voltage that is less than the reference voltage for the second logical value. The sense logic may output the first logical value when the global bit line has the boosted voltage or may output the second logical value when the global bit line has the discharge voltage.

主权项

1. A domino SRAM (static random access memory), comprising:
a local bit line; a global bit line; an SRAM cell coupled to the global bit line through the local bit line and configured to store one of a first logical value or a second logical value; precharge logic configured to precharge the global bit line to a non-zero precharge voltage for a period prior to a non-read operation and configured to charge the global bit line to a boosted voltage that is greater than the precharge voltage for a period prior to a read operation; discharge logic configured to maintain the global bit line at the boosted voltage for the read operation when reading the first logical value stored on the SRAM cell and configured to discharge the global bit line to a discharge voltage that is less than the precharge voltage for the read operation when reading the second logical value stored on the SRAM cell; and sense logic configured to output the first logical value when the global bit line is at the boosted voltage and configured to output the second logical value when the global bit line is at the discharge voltage.