| 主权项 |
1. A semiconductor device comprising: a die pad; a semiconductor chip; a plurality of leads; a plurality of conductive members; and a sealing body,
the die pad including:
an upper surface having a quadrangular shape in plan view;a chip bonding region having a quadrangular shape in plan view and being provided on the upper surface;a first groove being formed at a first corner portion of the chip bonding region;a second groove being formed at a second corner portion opposed to the first corner portion so as to interpose a center portion where two diagonal lines of the chip bonding region intersect with each other in a plan view;a third groove being formed at a third corner portion of the chip bonding region;a fourth groove being formed at a fourth corner portion opposed to the third corner portion so as to interpose the center portion of the chip bonding region in plan view; anda lower surface on an opposite side from the upper surface, the semiconductor chip including:
a first main surface having a quadrangular shape in plan view;a plurality of electrode pads formed on the first main surface; anda second main surface on an opposite side from the first main surface, the semiconductor chip having an outer-shape size smaller than an outer-shape size of the die pad in plan view and being mounted on the chip bonding region of the die pad so as to interpose a die-bond material; the plurality of leads being arranged along a periphery of the die pad; the plurality of conductive members electrically connecting the plurality of electrode pads of the semiconductor chip with the plurality of leads, respectively; the sealing body sealing the semiconductor chip, the plurality of conductive members, and the die pad, each of the first groove and the second groove being formed along a first direction intersecting with a first diagonal line which connects between the first corner portion and the second corner portion of the chip bonding region in plan view, each of the third groove and the fourth groove being formed along a second direction intersecting with a second diagonal line of the chip bonding region which intersects with the first diagonal line in plan view, each of the first groove, the second groove, the third groove, and the fourth groove being formed in a region overlapped with the semiconductor chip and in a region not overlapped with the semiconductor chip in plan view, each of the first groove, the second groove, the third groove, and the fourth groove being formed shallower than a thickness of the die pad, the semiconductor chip having a linear expansion coefficient different from a linear expansion coefficient of the die pad, and the die-bond material being arranged at the center portion, the first corner portion, the second corner portion, the third corner portion, and the fourth corner portion of the chip bonding region. |
