Methods for integrated circuit fabrication with protective coating for planarization

摘要

Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

主权项

1. A method of fabricating an integrated circuit, the method comprising:
forming a top surface of a first region of the integrated circuit at a higher level than a top surface of a second region of the integrated circuit; depositing a filler material over the top surface of the first region and over the top surface of the second region; depositing a protective material over the filler; and planarizing the filler material by performing a multi-part etch process, a first part of the multi-part etch process including an etch chemistry selective for the protective material, and a second part of the multi-part etch process including an etch chemistry selective for the filler material, wherein an etch rate of the protective material is higher than an etch rate of the filler material during the first part and wherein an etch rate of the filler material is higher than an etch rate of the protective material during the second part.