Compressive strained III-V complementary metal oxide semiconductor (CMOS) device

摘要

A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.

主权项

1. A method of forming a semiconductor device comprising:
forming a first III-V semiconductor layer on a semiconductor substrate; forming a second III-V semiconductor layer on the first III-V semiconductor layer, wherein the second III-V semiconductor layer has a bottommost surface that is in direct physical contact with a topmost surface of said first III-V semiconductor layer and has a greater lattice dimension than the first III-V semiconductor layer, wherein a compressive strain is formed in the second III-V semiconductor layer; and forming a p-type semiconductor device on the second III-V semiconductor layer having the compressive strain, wherein an entirety of a bottommost surface of a gate dielectric material of said p-type semiconductor device directly contacts a topmost surface of said second III-V semiconductor layer.