Method for selectively removing a spacer in a dual stress liner approach

摘要

By integrating a spacer removal process into the sequence for patterning a first stress-inducing material during a dual stress liner approach, the sidewall spacer structure for one type of transistor may be maintained, without requiring additional lithography steps.

主权项

1. A method, comprising:
forming a dielectric layer stack above a first transistor and a second transistor, said dielectric layer stack comprising a first stress-inducing layer and an etch control layer formed above said first stress-inducing layer; performing an etch sequence for selectively removing a portion of said dielectric layer stack from above said second transistor; concurrently recessing metal silicide regions in the second transistor and reducing a size of sidewall spacer structure formed on sidewalls of a gate electrode structure of said second transistor, while maintaining a sidewall spacer structure formed on sidewalls of a gate electrode structure of said first transistor; forming a second stress-inducing layer above said first and second transistors; and removing a portion of said second stress-inducing layer from above said first transistor by using said etch control layer as an etch stop material.