MOS device with isolated drain and method for fabricating the same

摘要

A method for fabricating a metal-oxide-semiconductor (MOS) device, performing operations of: forming a first well region embedded in a portion of a semiconductor substrate; forming a first patterned mask layer over the semiconductor substrate; performing a first ion implant process on two portions of the semiconductor substrate exposed by the first patterned mask layer; removing the first patterned mask layer and forming a second patterned mask layer over the semiconductor substrate, exposing a portion of the third well region; performing a second ion implant process to the portion of the third well region exposed by the second patterned mask layer; performing a third implant process to the portion of the third well region exposed by the second patterned mask layer; forming a source region in a portion of the third well region; and forming a drain region in a portion of the fifth well region.

主权项

1. A method for fabricating a metal-oxide-semiconductor (MOS) device with isolated drain, comprising:
providing a semiconductor substrate having a first conductivity type; forming a first well region embedded in a portion of the semiconductor substrate, having a second conductivity type opposite to the first conductivity type; forming a first patterned mask layer over the semiconductor substrate, exposing two portions of the semiconductor substrate, wherein the two portions of the semiconductor substrate are separated from each other by the first patterned mask layer; performing a first ion implant process on the two portions of the semiconductor substrate exposed by the first patterned mask layer, forming two second well regions in the semiconductor substrate and defining a third well region in the semiconductor substrate, wherein the second well regions are isolated from each other by the third well region and overlie the first well region, and the second well regions have the second conductivity type, and the third well region has the first conductivity type; removing the first patterned mask layer and forming a second patterned mask layer over the semiconductor substrate, exposing a portion of the third well region; performing a second ion implant process to the portion of the third well region exposed by the second patterned mask layer, forming a fourth well region between the first well region and the portion of the third well region exposed by the second patterned mask layer, wherein the fourth well region has the first conductivity type; performing a third implant process to the portion of the third well region exposed by the second patterned mask layer, forming a fifth well region overlying the fourth well region and being adjacent to other portions of the third well region covered by the second patterned mask layer, wherein the fifth well region has the second conductivity type; removing the second patterned mask layer and forming a gate stack over the semiconductor substrate, covering a portion of the third and fifth well regions; forming a source region in a portion of the third well region; and forming a drain region in a portion of the fifth well region.