Dual-port positive level sensitive preset data retention latch

摘要

In an embodiment of the invention, a dual-port positive level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.

主权项

1. A dual-port positive level sensitive preset data retention latch comprising:
a clocked inverter configured to receive a first data bit (D1), clock signal (CKT), a binary logical compliment clock signal (CLKZ), a preset control signal (PRE) and a binary logical compliment retention mode control signal (RETN), wherein CKT, CLKZ, RETN and PRE determine whether a data output (QN) from the clocked inverter is the binary compliment of the first data bit (D1) or an indeterminate value; a dual-port latch configured to receive the data output (QN) of the clocked inverter, a second data bit (D2), the clock signal (CKT), the binary logical compliment clock signal (CLKZ), the retain control signal (RET) and the binary logical compliment retain control signal (RETN), a preset control signal (PRE), a latch control signal (SS) and a binary control compliment latch control signal (SSN) wherein signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the data output (QN) of the clocked inverter or the second data bit (D2) is latched in the dual-port latch.