发明名称 Nonvolatile semiconductor memory device and method for manufacturing the same
摘要 According to one embodiment, a nonvolatile semiconductor memory device includes a silicon-containing substrate, a plurality of memory cells, and an insulating film. The substrate includes silicon. The plurality of memory cells is provided on the substrate with a spacing therebetween. The insulating film is provided on a sidewall of the memory cell. The insulating film includes a protrusion protruding toward an adjacent one of the memory cells above a void portion is provided between the memory cells.
申请公布号 US9006815(B2) 申请公布日期 2015.04.14
申请号 US201213351424 申请日期 2012.01.17
申请人 Kabushiki Kaisha Toshiba 发明人 Oda Tatsuhiro
分类号 H01L29/788;H01L21/3205;H01L21/4763;H01L21/28;H01L21/764;H01L27/115;H01L29/423 主分类号 H01L29/788
代理机构 Oblon, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A nonvolatile semiconductor memory device comprising: a silicon-containing substrate; a plurality of memory cells provided on the substrate with a spacing therebetween; and an insulating film including a first silicon oxide film and a second silicon oxide film, the first silicon oxide film provided on a sidewall of the memory cell, and on a surface of the silicon-containing substrate between the memory cells, the second silicon oxide film provided on the first silicon oxide film above a void portion provided between the memory cells, the second silicon oxide film including a protrusion protruding toward an adjacent one of the memory cells, a material of the second silicon oxide film being same as a material of the first silicon oxide film; the memory cells including: a tunnel insulating film provided on the substrate;a floating gate provided on the tunnel insulating film;an intergate insulating film provided on the floating gate; anda control gate provided on the intergate insulating film; the protrusion is provided above an upper surface of the floating gate; and a height of an upper end of the protrusion is lower than a height of an upper end of the control gate.
地址 Tokyo JP