发明名称 |
Method of forming semiconductor device having metal gate |
摘要 |
A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench. |
申请公布号 |
US9006091(B2) |
申请公布日期 |
2015.04.14 |
申请号 |
US201414302047 |
申请日期 |
2014.06.11 |
申请人 |
United Microelectronics Corp. |
发明人 |
Tsai Shih-Hung;Fu Ssu-I;Chen Ying-Tsung;Chen Chih-Wei;Lin Chien-Ting;Chiang Wen-Tai |
分类号 |
H01L21/338;H01L29/66;H01L21/283;H01L21/28;H01L21/762;H01L29/78;H01L29/51 |
主分类号 |
H01L21/338 |
代理机构 |
J.C. Patents |
代理人 |
J.C. Patents |
主权项 |
1. A method of forming a semiconductor device, comprising:
forming a first interfacial material layer by a deposition process on a substrate; forming a dummy gate material layer on the first interfacial material layer; patterning the dummy gate material layer and the first interfacial material layer to form a stacked structure; forming an interlayer dielectric (ILD) layer to cover the stacked structure; removing a portion of the ILD layer to expose a top of the stacked structure; removing the stacked structure to form a trench in the ILD layer; conformally forming a second interfacial layer and a first high-k layer at least on a surface of the trench; and forming a composite metal layer to at least fill up the trench, wherein the substrate is a bulk substrate without fins, and wherein the composite metal layer comprises a work function metal layer and a low resistivity metal layer, and further comprises: a bottom barrier layer, disposed between the first high-k layer and the work function metal layer; a top barrier layer, disposed between the work function metal layer and the low resistivity metal layer; and an etch stop metal layer, disposed between the bottom barrier layer and the work function metal layer. |
地址 |
Hsinchu TW |