| 主权项 |
1. A circuit for forward error correction (FEC) decoding, comprising:
a decoding pipeline that includes a plurality of decoding stages and is configured to receive a data block that includes a plurality of data symbols, encoded with a Reed-Solomon (RS) FEC coding thereafter further encoded by a second FEC coding, a first set of FEC datagrams for correcting respective received words of the plurality of data symbols encoded with the RS FEC coding, and a second set of FEC datagrams for correcting respective received words of the plurality of data symbols encoded with the second FEC coding, each decoding stage configured to:
decode the plurality of data symbols with the second FEC coding using the second set of FEC datagrams; anddecode the plurality of data symbols with the RS FEC coding using the first set of FEC datagrams; and a post-processing circuit coupled to an output of the decoding pipeline and configured to, in response to one of the second set of FEC datagrams indicating one of the respective received words of the plurality of data symbols encoded with the second FEC coding includes data symbols in error, perform bitwise RS decoding of ones of the plurality of data symbols in error by performing operations including:
retrieving RS syndromes, generated in the decoding the plurality of data symbols with the RS FEC coding, corresponding to symbols of the one of the respective received words that contain errors;determining an inverse matrix that is an inverse of corresponding columns of a parity check matrix (H), based on a first index of the one of the received words encoded with second FEC coding in error;multiplying the inverse matrix with the RS syndromes to determine locations of bits in error; andcorrecting bits at the determined locations of the bits in error. |
