| 摘要 |
Using relatively inexpensive, external resistor networks, an electronic device, such as an FPGA, can be configured to use non-MIPI interfaces to communicate with one or more MIPI-compliant devices, such as video sources (e.g., cameras) and sinks (e.g., displays). High-speed (HS) and low-power (LP) MIPI signaling for each MIPI clock/data lane is supported by a set of one or more non-MIPI interfaces, such as LVDS and/or LVCMOS receivers, transmitters, and/or transceivers, and an appropriate, corresponding, external resistor network. For configurations in which the resistor-configured electronic device can handle high-speed MIPI data from a MIPI-compliant device, the electronic device can detect transitions in the MIPI mode of the MIPI-compliant device. In some configurations, the resistor-configured electronic device can provide high-speed MIPI data to a MIPI-compliant device. In either case, the electronic device configures the non-MIPI interfaces to support the current MIPI HS/LP mode. |
| 主权项 |
1. An electronic system comprising:
an integrated circuit comprising a plurality of non-MIPI (Mobile Industry Processor Interface) interfaces; a clock-lane resistor network connected to a first set of one or more non-MIPI interfaces of the integrated circuit, wherein the clock-lane resistor network enables the first set to be connected, via the clock-lane resistor network, to and communicate with a MIPI-compliant device via a clock lane; and a first data-lane resistor network connected to a second set of one or more non-MIPI interfaces of the integrated circuit, wherein the first data-lane resistor network enables the second set to be connected, via the first data-lane resistor network, to and communicate with the MIPI-compliant device via a first data lane, wherein:
the MIPI-compliant device is configured to operate in a MIPI high-speed (HS) mode or a MIPI low-speed (LP) mode;the second set of non-MIPI interfaces comprises first and second single-ended interfaces for communication in the MIPI LP mode and a differential interface for communication in the MIPI HS mode; andthe first data-lane resistor network comprises:
a first resistor connected between a first wire of the first data lane and the first single-ended interface; anda second resistor connected between a second wire of the first data lane and the second single-ended interface. |
