Apparatus, method and program for design validity verification of electronic circuit board with regard to power supply noise suppression

摘要

Disclosed is a method for design validity verification of an electronic circuit board with regard to power supply noise, wherein with regard to an i-th LSI (i=1 to n) on the electronic circuit board, an input voltage Vin[i] to the LSI from the printed circuit board is given by Vin[i]=VDD−Z1si[i]×VDD/(Z1si[i]+Z11[i]), where Z1si[i] is an input impedance characteristic and Z11[i] is a reflected impedance characteristic viewed from a position at which the i-th LSI is mounted, being a characteristic with the i-th LSI omitted from the whole of the electronic circuit board and a judgment is made as to whether or not a reflected voltage Vr[i]=Vin[i]×(Z1si[i]+Z11[i])/(Z1si[i]−Z11[i]) satisfies |Vr[i]|≦Δ V (power supply variation tolerance range).

主权项

1. A computer-implemented method of verifying design validity of an electronic circuit board on which a semiconductor device is mounted, the computer-implemented method comprising:
determining an amplitude of an input voltage to be applied from an electronic circuit board side to the semiconductor device based on a power supply voltage and characteristic impedances of the semiconductor device and the electronic circuit board; applying the input voltage to the semiconductor device from the electronic circuit board side; obtaining a reflected voltage at the semiconductor device with respect to the input voltage inputted to the semiconductor device from the electronic circuit board side, using a reflection coefficient determined based on associated characteristic impedances of the semiconductor device and the electronic circuit board; and comparing an absolute value of the reflected voltage with a predetermined tolerance range of power supply variation that assures operation of the semiconductor device and making a judgment as to whether or not the reflected voltage is within the tolerance range of power supply variation to perform verification of design validity.