发明名称 |
2-transistor flash memory and programming method of 2-transistor flash memory |
摘要 |
Disclosed is a 2-transistor flash memory that includes a memory cell array, a row driver, a read/write circuit, a charge pump generating a high voltage, and control logic configured to transfer the high voltage to the row driver, the read/write circuit, and the memory cell array. If programming, the row driver and the read/write circuit apply voltages such that a control gate of a cell transistor in an unselected memory cell on a different row from a selected memory cell is floated. |
申请公布号 |
US9007833(B2) |
申请公布日期 |
2015.04.14 |
申请号 |
US201213618263 |
申请日期 |
2012.09.14 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Jeon Chang Min;Park Weonho;Kim Byoungho |
分类号 |
G11C11/34;G11C16/04 |
主分类号 |
G11C11/34 |
代理机构 |
Harness, Dickey & Pierce, P.L.C. |
代理人 |
Harness, Dickey & Pierce, P.L.C. |
主权项 |
1. A 2-transistor flash memory comprising:
a memory cell array including a plurality of memory cells each having a pair of (1) a cell transistor and (2) a selection transistor connected to the cell transistor in series; a row driver connected to cell transistors of memory cells on a same row via global control lines and byte selection transistors, the row driver connected to selection transistors of memory cells on the same row via word lines; a read/write circuit connected to each of the plurality of memory cells on a same column via global bit lines and sector selection transistors, the read/write circuit configured to control the byte selection transistors via byte control lines; a charge pump configured to generate a positive high voltage; and control logic configured to transfer the positive high voltage to the row driver, the read/write circuit, and the memory cell array, wherein when programming, the row driver and the read/write circuit are configured to apply voltages such that a control gate of a cell transistor in an unselected memory cell on a different row from a selected memory cell is floated. |
地址 |
Gyeonggi-Do KR |