发明名称 Method of making a semiconductor device having a post-passivation interconnect structure
摘要 A method of making a semiconductor device includes forming a passivation layer overlying a semiconductor substrate, the semiconductor substrate having a first region and a second region, wherein the first region is a conductive pad and the second region is adjacent to the first region. The method further includes forming a first protective layer overlying the passivation layer and forming an interconnect layer overlying the first protective layer. The method further includes forming a plurality of slots in the second region and forming a second protective layer overlying the interconnect layer, wherein the second protective layer fills each slot of the plurality of slots. The method further includes exposing a portion of the interconnect layer through the second protective layer; forming a barrier layer on the exposed portion of the interconnect layer; and forming a solder bump on the barrier layer.
申请公布号 US9006891(B2) 申请公布日期 2015.04.14
申请号 US201314058466 申请日期 2013.10.21
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Liang Shih-Wei;Chen Hsien-Wei;Chen Ying-Ju;Yu Tsung-Yuan;Lii Mirng-Ji
分类号 H01L29/40;H01L23/10;H01L23/48;H01L21/44;H01L23/00;H01L23/31;H01L21/768;H01L23/525 主分类号 H01L29/40
代理机构 Lowe Hauptman & Ham, LLP 代理人 Lowe Hauptman & Ham, LLP
主权项 1. A method of making a semiconductor device, the method comprising: forming a passivation layer overlying a semiconductor substrate, the semiconductor substrate having a first region and a second region, wherein the first region is a conductive pad and the second region is adjacent to the first region; forming a first protective layer overlying the passivation layer; forming an interconnect layer overlying the first protective layer; forming a plurality of slots in the second region; forming a second protective layer overlying the interconnect layer, wherein the second protective layer fills each slot of the plurality of slots; exposing a portion of the interconnect layer through the second protective layer; forming a barrier layer on the exposed portion of the interconnect layer; and forming a solder bump on the barrier layer.
地址 TW
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