Nonvolatile semiconductor memory device and method for manufacturing the same

摘要

In general, according to one embodiment, a nonvolatile semiconductor memory device includes a memory cell region and a peripheral region. The memory cell region includes first element isolation regions, first semiconductor regions, a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate electrode. The first element isolation regions separate a semiconductor layer and include a first insulating film. The first semiconductor regions are separated by the first element isolation regions. The peripheral region includes a second element isolation region a second insulating film. Each of the first element isolation regions includes a first and a second portion. A step is present between the first and the second portion. At least part of a side surface and a lower end of the second element isolation region are surrounded by the semiconductor layer.

主权项

1. A nonvolatile semiconductor memory device comprising a memory cell region and a peripheral region,
the memory cell region including:
a plurality of first element isolation regions separating a semiconductor layer in a second direction crossing a first direction, the first element isolation regions including a first insulating film;a plurality of first semiconductor regions separated by the first element isolation regions in the second direction and extending in the first direction; anda first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate electrode provided on the first semiconductor regions, the peripheral region including:
a second element isolation region separating the semiconductor layer into a plurality of second element regions and including a second insulating film, wherein each of the first element isolation regions includes a first portion and a second portion provided under the first portion, a step is disposed between the first portion and the second portion, at least part of a side surface and a lower end of the second element isolation region are surrounded by the semiconductor layer.