Dual-mode capacitive transimpedance amplifier, and read-out device incorporating the same

摘要

A capacitive transimpedance amplifier for a detector unit capable of generating first and second detection currents comprises: a read-out circuit including an integration capacitor coupled between an input node connected to the detector unit, and a common node between first and second transistors connected in series, and a sampling and holding unit coupled between the first common node and an output node for sampling and holding a voltage at the first common node; and a switch unit connected to control ends of the first and second transistors and the input node, and operable between a first state, where the first detection current is read out, and a second state, where the second detection current is read out.

主权项

1. A capacitive transimpedance amplifier for a detector unit capable of generating first and second detection currents flowing respectively in opposite directions, said capacitive transimpedance amplifier comprising:
a read-out circuit having an input node adapted to be connected electrically to the detector unit, and an output node, and including
an integration capacitor having a first end coupled to said input node, and a second end,first and second transistors adapted to be connected in series between first and second reference potentials, a first common node between said first and second transistors being coupled to said second end of said integration capacitor, each of said first and second transistors having a control end, anda sampling and holding unit coupled between said first common node and said output node for sampling and holding a voltage at said first common node; and a switch unit adapted to be connected between third and fourth reference potentials, and connected electrically to said control ends of said first and second transistors and said input node of said read-out circuit; wherein said switch unit is operable between a first state, where said control ends of said first and second transistors are coupled respectively to said input node and the fourth reference potential through said switch unit such that the first detection current from the detector unit is read out by said read-out circuit, and a second state, where said control ends of said first and second transistors are coupled respectively to the third reference potential and said input node through said switch unit such that the second detection current from the detector unit is read out by said read-out circuit.