发明名称 Post-mold for semiconductor package having exposed traces
摘要 Method of and devices for protecting semiconductor packages are provided. The methods and devices comprise loading a leadframe containing multiple semiconductor packages into a molding device, adding a molding material on a surface of the leadframe, molding the molding material, such that the molding material covers the entire surface of the semiconductor packages except conducting terminals, and singulating the semiconductor packages from the leadframe after molding the molding material.
申请公布号 US9006034(B1) 申请公布日期 2015.04.14
申请号 US201213689566 申请日期 2012.11.29
申请人 UTAC Thai Limited 发明人 Sirinorakul Saravuth
分类号 H01L23/31;H01L21/56;H01L21/48 主分类号 H01L23/31
代理机构 Haverstock & Owens LLP 代理人 Haverstock & Owens LLP
主权项 1. A method of forming a protective layer on partially molded semiconductor packages comprising: a. adding a molding material on a surface of the semiconductor packages on a leadframe; b. selectively covering a first conductive member with the molding material by using a molding device, such that the first conductive member becomes a protected first conductive member; c. preventing the molding material from covering at least one conductive terminal by making a contact of a mold chase with a bottom side of the at least one conductive terminal while the molding material is applied to one or more cavities between the mold chase and the first conductive member; and d. forming a protective surface covering substantial all of the surface of the semiconductor packages.
地址 Bangkok TH
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