Adaptive phase-shifted synchronization clock generation circuit and method for generating phase-shifted synchronization clock

摘要

The present invention discloses an adaptive phase-shifted synchronization clock generation circuit and a method for generating phase-shifted synchronization clock. The adaptive phase-shifted synchronization clock generation circuit includes: a current source generating a current which flows through a node to generate a node voltage on the node; a reverse-proportional voltage generator coupled to the node for generating a voltage which is reverse-proportional to the node voltage; a ramp generator receiving a synchronization input signal and generating a ramp signal; a comparator comparing the reverse-proportional voltage to the ramp signal; and a pulse generator for generating a clock signal according to an output from the comparator.

主权项

1. An adaptive phase-shifted synchronization clock generation circuit, comprising:
a current-to-voltage converter circuit coupled to a phase setting node; and a plurality of circuit modules each including:
at least one current source generating and determining a current which flows through a node to generate a node voltage on the node;an inverse-proportional voltage generator coupled to the node for generating a voltage which is inverse-proportional to the node voltage;a ramp generator receiving a synchronization input signal from a synchronization signal input pin and generating a ramp signal;a comparator comparing the inverse-proportional voltage to the ramp signal; anda pulse generator for generating a clock signal according to an output from the comparator, the clock signal being provided as an internal clock signal of the corresponding circuit module and outputted from a synchronization signal output pin as a synchronization output signal; wherein the node voltage is proportional to a total number of the circuit modules coupled to the node, and the inverse-proportional voltage is inverse-proportional to the total number of the circuit modules coupled to the node, whereby a phase difference between the synchronization output signal and the synchronization input signal of each of the circuit modules is automatically adjusted according to the inverse-proportional voltage; and wherein the synchronization signal input pin of the first one of the circuit modules receives a system clock and the synchronization signal input pin of each of the other circuit modules receives the synchronization output signal from the previous circuit module as the synchronization input signal of the present circuit module.