发明名称 Digital phase equalizer for serial link receiver and method thereof
摘要 An apparatus of automatic power control for burst mode laser transmitter and method are provided. In one implementation a method includes: pushing a first multi-bit data into a data memory; modifying the data memory to remove a condition of frequent transition in the data memory, if the condition of frequent transition is found; establishing a list of indices pointing to data transition of the data memory; and sequentially examining a respective run length of the data indexed by each entry in the list, modifying the associated data to lengthen the respective run length if the respective run length is too short, modifying the associated data to shorten the respective run length if the respective run length is too long, and outputting a second multi-bit data by taking data from the data memory.
申请公布号 US9008165(B2) 申请公布日期 2015.04.14
申请号 US201213347888 申请日期 2012.01.11
申请人 Realtek Semiconductor Corp. 发明人 Lin Chi-Liang
分类号 H03H7/30;H04L25/03 主分类号 H03H7/30
代理机构 McClure, Qualey & Rodack, LLP 代理人 McClure, Qualey & Rodack, LLP
主权项 1. An apparatus for equalizing a continuous-time signal comprising: a serial-to-parallel over-sampler configured to receive the continuous-time signal and output a first multi-bit data, and an equalizer, coupled to the serial-to-parallel over-sampler, configured to: receive the first multi-bit data; detect and remove a condition of bubble transition in the first multi-bit data to produce a modified multi-bit data, wherein a bubble transition is defined by more than two transitions within consecutive samples of a sample length that is proportional to an oversampling ratio of the serial-to-parallel over-sampler; establish a list of indices pointing to locations of data transitions in the modified multi-bit data; sequentially examine a respective run length of the data indexed by each entry in the list; modify associated data to lengthen the run length in response to a determination that the run length is too short and to shorten the run length in response to a determination that the run length is too long; and output a second multi-bit data.
地址 Hsinchu TW
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