Structure and method of T_invscaling for high k metal gate technology

摘要

A complementary metal oxide semiconductor structure including a scaled 0 and a scaled pFET which do not exhibit an increased threshold voltage and reduced mobility during operation is provided. The method includes forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack can also be plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion contains up to 15 atomic % N2 and an nFET threshold voltage adjusted species, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion contains up to 15 atomic % N2 and a pFET threshold voltage adjusted species.

主权项

1. A complementary semiconductor (CMOS) structure comprising:
a semiconductor substrate having an nFET device region and a pFET device; and an nFET gate stack located in the nFET device region and a pFET gate stack located in the pFET device region, wherein the nFET gate stack includes, from bottom to top, a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion comprising a combination of a metal oxide component, a rare earth metal ion or an alkaline earth metal ion, and up to 15 atomic % N2, and a first patterned portion of a gate electrode layer, and the pFET gate stack includes, from bottom to top, a plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion comprising said metal oxide component, an ion selected from the group consisting of Ti, Ta, Al and Ge and up to 15 atomic % N2, and a second patterned portion of a gate electrode layer.